1. Field of the Invention
The present invention relates in general to a charged-device-model (CDM) electrostatic discharge (ESD) protection device, and especially to a CDM ESD protection device using deep N-well structure.
2. Description of the Related Art
ESD protection circuits are generally known to protect integrated circuits (IC) from machine model (MM) or human body model (HBM) electrostatic discharge events. In an HBM or MM mode electrostatic discharge event, electrostatic charges enter the IC through some of the IC pins and exit through others. To protect IC from such ESD events, an ESD protection circuit is often disposed adjacent to the output or input pad of the IC circuit to discharge the ESD stress. As the conventional ESD protection circuit shows in FIG. 1, the components of the input buffer 12 are protected against ESD events. The two-stage ESD protection circuit 10 has a secondary ESD protection circuit 14, a primary ESD protection circuit 16 and a resistor R. The secondary ESD protection circuit 14 clamps the electrostatic stress across the input buffer 12; and the primary ESD protection circuit 16 discharges the electrostatic stress. Via proper design, the input buffer 12 is effectively protected from the HMB and MM ESD events.
Apart from the HMB and MM ESD events described, another ESD type referred to is charged-device model (CDM). In a CDM ESD event, electrostatic charges are stored in a floating IC substrate and are discharged via the momentarily grounded pins. Unlike HBD or MM ESD events, the ESD charges of a CMD ESD event are stored in the IC substrate, not relying on an external source. For instance, electrostatic charges accumulate in the IC via friction generated during IC conveyance. When one or more pins of the IC are momentarily grounded to a grounded platform, the electrostatic charges are discharged through the grounded pins.
The schematic diagrams of IC with the positive and the negative charges in a floating substrate are respectively shown in FIGS. 2 and 3. Because the IC is in a floating state, the accumulated electrostatic charges (as the positive charges 11 in FIG. 2 and the negative charges 13 in FIG. 3), due to the repelling characteristics of equal polarity, distribute evenly on the IC or IC substrate 20. The components of IC are usually only several micrometers thick on the wafer surface. For example, in a 0.35 micrometer CMOS process, the N-type or P-type well 22 is only about 2 micrometers thick, the N+ diffusion 26 and the P+ diffusion 24 is about 0.2 micrometer thick only. The substrate 20 has a much greater thickness, about 500˜600 micrometers, depending on the overall wafer thickness. Therefore, the majority of the electrostatic charges are accumulated in the substrate 20 of the IC, as shown in FIGS. 2 and 3.
CDM ESD stress often breaks through the gate oxide layers of input buffers. The substrate is filled with a substantial amount of electrostatic charges which transiently cause overstress and breakdown of the gate oxide of the input buffers. IESD in FIGS. 2 and 3 represents the schematic CDM ESD current path. The schematic equivalent circuit diagram of the discharge operation is shown in FIG. 4. Although an ESD protection circuit 10 is added beside the input pad 18 connected to the input buffer, the gate oxide 30 of the input buffer is still easily broken down in a CDM ESD event. Because the CDM charges 32 are initially stored in the IC substrate, the ESD protection circuit 10 beside the input pad 18 cannot discharge the CDM charges as quickly as in a HMB or MM event wherein the electrostatic charges are provided externally. Conventional ESD protection circuits endure high HMB or MM ESD stress, but cannot cope with this CDM ESD stress.
A conventional method solves the problems caused by CDM ESD events by adding a small gate-grounded NMOS bedside the gate of the input buffer. The ground line VSS connected to the small gate-grounded NMOS is also the ground line of the input buffer as shown in FIG. 5, the schematic CDM ESD protection circuit diagram, wherein Mn1b and Mp1a are small gate-grounded MOS for clamping the CDM ESD stress across the gate of the input buffer. The other CDM ESD protection design is shown in FIG. 6, wherein two small diodes (Dp and Dn) are used to clamp the CDM ESD stress across the gate of the input buffer. In both cases, the added components Mp1a, Mn1b or Dp, Dn have to be formed inside the IC along with the input buffer to effectively protect the IC from CDM ESD stress. Such a design, on the other hand, produces IC more susceptible to the latch-up effect.
The other conventional method to solve the CDM ESD problem is to dispose the input buffer beside the pad so that the gate oxide of input buffer is protected by the HMB/MM ESD protection circuit near the pad. However, this will increase the layout complexity of the circuit around the pad.
In U.S. Pat. No. 5,901,022, an inductor is added between the input pad and the HBM/MM ESD protection circuit to clamp the CDM ESD stress across the gate oxide of the input buffer.
In U.S. Pat. No. 5,729,419, a CDM ESD protection circuit is proposed for the output buffer to clamp the voltage across the gate oxide of the output buffer.